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Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries
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Involve in NVM architecture for optimum performance and area
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Design and verify the new circuits to handshake with the analog computation blocks
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Design, optimize and verify the NVM circuits including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits
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Participate in RNM and functional model of NVM circuits for verification
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Responsible for verifying the functional blocks and full chip level interfacing with NVM design
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Work closely with the validation engineers to expedite the silicon evaluation process
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Work closely with backend teams for the production qualification releases
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Ph.D. or MS degree in EE or related 5-10+ years industrial experience
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Hands-on experience in NVM embedded or NVM product design and verification
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Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification
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Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling
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Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability
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Good understanding & knowledge of semiconductor device physics, and advanced process technology
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Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging
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Excellent communication skills, ability to work well across multi-functional teams
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Fluent in all major CAD tools: SPICE, Cadence, Verilog simulation software
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Some knowledge of scripting such as Python
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Must be a self-starter, detail-oriented, and team player