Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
About the role
Efficient Computer is building a new energy-efficient processor architecture from the ground up. As a Silicon Engineering Intern, you'll join our hardware team and work on production silicon, not a sandbox project. Each intern owns a well-scoped project, has a dedicated mentor, and presents results to the engineering team at the end of the internship.
What you'll do
- Help define micro-architecture for blocks and features, and implement RTL in SystemVerilog.
- Turn specs into verification plans, build testbench components, and write and debug tests.
- Run synthesis, place-and-route and timing analysis, and evaluate power, performance and area trade-offs.
- Build and improve design, verification and implementation flows, including automation and AI-assisted tooling.
- Work with architecture, design and verification engineers to find and fix issues before tapeout.
Required qualifications
- Currently pursuing a BS, MS or PhD in Electrical Engineering or Computer Engineering with graduation expected by Summer 2028.
- At least one term of school remaining after summer 2027.
- Coursework or project experience in digital logic design, verification, VLSI/physical design, or EDA tooling.
- Experience with at least one programming or scripting language, such as Python, C/C++, Tcl or Perl.
How to stand out
- Coursework in computer architecture.
- Verilog and System Verilog proficiency
- Experience with synthesis, static timing analysis, or place-and-route tools
- Experience with simulators and waveform debug
- FPGA design experience
- Interest in applying LLMs/agents to engineering workflows.
Details
- Duration: 12 weeks onsite, Summer 2027, then fulltime onsite/ part time onsite/ part time remote in Fall 2027
- Location: On-site in Austin, TX, San Jose, CA or Pittsburgh, PA
Why Join Efficient?
Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.