ARSIEM Corporation

388 Senior Hardware/Software Design Engineer

ARSIEM Corporation · Annapolis Junction, MD
Annapolis Junction, MD $167K–$187K Posted 2026-06-19
Salary
$167K–$187K
Type
Full-time
Experience
5+ yr

About ARSIEM Corporation

At ARSIEM Corporation we are committed to fostering a proven and trusted partnership with our government clients.  We provide support to multiple agencies across the United States Government.  ARSIEM has an experienced workforce of qualified professionals committed to providing the best possible support.

As demand increases, ARSIEM continues to provide reliable and cutting-edge technical solutions at the best value to our clients.  That means a career packed with opportunities to grow and the ability to have an impact on every client you work with.

ARSIEM is looking for an Operational Systems Integrator 3 (Network Designer/Architect 3). This position will support one of our government clients in Fort Meade, MD.

Clearance Requirement: This position requires an active TS/SCI with a polygraph. You must be a U.S. citizen for consideration.

Candidate Referral: Do you know someone who would be GREAT at this role? If you do, ARSIEM has a way for you to earn a bonus through our referral program for persons presenting NEW (not in our resume database) candidates who are successfully placed on one of our projects. The bonus for this position is $5,000, and the referrer is eligible to receive the sum for any applicant we can place within 12 months of referral. The bonus is paid after the referred employee reaches six months of employment.

ARSIEM is proud to be an Equal Opportunity and Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other federally protected class.

  • Implement DSP and associated technical components in FPGA for code base integration.
  • Strong experience required for FPGA coding, Digital Signal Processing theory & application, Interfacing FPGA code with existing code bases and software.
  • Knowledge of signal processing blocks and related DSP components, Linux OS, coding ability in C and C++.
  • Bachelor's degree plus 8-years of relevant experience or equivalent.
  • Additional experience with Vivado required.
  • Experience with Epiq Solution PDK preferred.

The ARSIEM pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) job responsibilities, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other laws.

Benefits:
For an overview of our benefits, please visit our benefits tab.
https://www.arsiem.com/careers/

Original Posting Date:
2026-06-23

$110K — 10th pctl $265K — 90th pctl
This role’s midpoint $177K vs. market median $185K for Engineering roles
~median
market rate
Based on 14,000+ Engineering roles with disclosed salary ranges tracked on NewJob.
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