SOC Design Verification Engineer

We are seeking an experienced SoC Design Verification Engineer  with a strong background in UVM-based verification  and SystemVerilog  to join our dynamic engineering team. The ideal candidate will have hands-on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.

Key Responsibilities:


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Develop, implement, and maintain UVM-based verification environments  for SoC and IP-level designs.


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Write and execute SystemVerilog assertions  to validate design functionality and performance.


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Integrate C/C++ reference models  within verification testbenches and ensure seamless co-simulation.


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Perform debugging at IP and subsystem levels , identifying and resolving functional and timing issues.


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Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals.


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Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure.


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Participate in regression management, bug tracking, and documentation for design verification deliverables.



Required Qualifications:


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Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field .


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10+ years  of hands-on experience in SoC or IP-level design verification .


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Strong proficiency in SystemVerilog , UVM methodology , and assertion-based verification (ABV) .


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Experience integrating C/C++ models  in verification environments.


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Proven debugging skills  at both IP and subsystem levels  using industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).



Good to Have:


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Gate-Level Simulation (GLS)  and post-silicon verification exposure.


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Experience with Low Power Verification (UPF / CPF)  methodologies.


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Familiarity with ARM-based SoC architectures  and interconnect verification.


 
  California Pay Range $160,000 — $180,000 USD